Performance comparison review of 32-bit multiplier designs
作者： Kelly Liew Suet Swee , Lo Hai Hiung
DOI: 10.1109/ICIAS.2012.6306130
关键词: 32-bit 、 Algorithm 、 Computer science 、 Standard cell 、 Application-specific integrated circuit 、 ModelSim 、 Multiplier (economics) 、 Verilog 、 Logic synthesis 、 Hardware description language
摘要: … -4 Booth Encoding multiplier has the best findings in the area performance in all three of the … Wallace multiplier exhibited the largest area performance instead of Dadda multiplier in the …
sci-hub.se 参考文章(2)
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K.C. Bickerstaff, E.E. Swartzlander, M.J. Schulte, Analysis of column compression multipliers symposium on computer arithmetic. pp. 33- 39 ,(2001) , 10.1109/ARITH.2001.930101