A Unique Low-Power Implementation of 4-2 Compressor in High Speed Multiplier

作者： A. H. Sharief , Sowjanya Kanna , S. Neelima

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摘要: On using these Compressors in the multiplier, number of interconnections gets reduced, which further produces quick results, along with consuming lesser power. The concept compressors for improving performance multiplier is done on transistor level. different designs compared and observation that usage compressor makes process more energy efficient faster as to traditional methods. delay power-delay product (PDP) earlier Wallace Dadda Multipliers, implemented 4-2 without compressors, proven have minimum PDP.

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参考文章(10)

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A Unique Low-Power Implementation of 4-2 Compressor in High Speed Multiplier

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A Unique Low-Power Implementation of 4-2 Compressor in High Speed Multiplier

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