Low-power low-voltage 4-2 compressors for VLSI applications

作者: M. Margala , N.G. Durdle

DOI: 10.1109/LPD.1999.750407

关键词: Low-power electronicsBiCMOSLow voltageCMOSElectrical engineeringElectronic engineeringEngineeringGas compressorElectronic circuitCapacitanceElectrical efficiency

摘要: This paper presents new 4-2 compressor architectures, a full-swing bipolar double pass-transistor compressor, BiNMOS reduced-swing and that outperform standard CMOS up to 3 times in power-efficiency at supply voltages 1.5 V-3 V. The is more power-efficient than even fanout of 1. All remaining proposed compressors have lower crossover capacitance with previously reported low-power compressors. Circuits were designed fabricated 0.8 /spl mu/m BiCMOS technology.

参考文章(11)
Yasuaki Iwase, Youji Kanie, Yasushi Kubota, Shuhei Tsuchimoto, Shinji Toyoyama, 4-2 Compressor with Complementary Pass-Transistor Logic IEICE Transactions on Electronics. ,vol. 77, pp. 647- 649 ,(1994)
Mohamed I. Elmasry, A.bdellatif Bellaouar, Jonathan Allen, Low-Power Digital VLSI Design: Circuits and Systems ,(1995)
Jan M. Rabaey, Massoud Pedram, Low Power Design Methodologies ,(2009)
Martin Margala, Nelson G. Durdle, 1.2 V full-swing BiDPL logic gate Microelectronics Journal. ,vol. 29, pp. 421- 429 ,(1998) , 10.1016/S0026-2692(97)00082-7
Shen-Fu Hsiao, Ming-Roun Jiang, Jia-Sien Yeh, Design of high-speed low-power 3-2 counter and 4-2 compressor for fast multipliers Electronics Letters. ,vol. 34, pp. 341- 343 ,(1998) , 10.1049/EL:19980306
G. Goto, T. Sato, M. Nakajima, T. Sukemura, A 54*54-b regularly structured tree multiplier IEEE Journal of Solid-state Circuits. ,vol. 27, pp. 1229- 1236 ,(1992) , 10.1109/4.149426
M. Suzuki, N. Ohkubo, T. Shinbo, T. Yamanaka, A. Shimizu, K. Sasaki, Y. Nakagome, A 1.5-ns 32-b CMOS ALU in double pass-transistor logic international solid-state circuits conference. ,vol. 28, pp. 1145- 1151 ,(1993) , 10.1109/4.245595
MARTIN MARGALA, NELSON G. DURDLE, Novel low-voltage low-power full-swing BiNMOS logic gate International Journal of Electronics. ,vol. 84, pp. 487- 498 ,(1998) , 10.1080/002072198134599
J. Mori, M. Nagamatsu, M. Hirano, S. Tanaka, M. Noda, Y. Toyoshima, K. Hashimoto, H. Hayashida, K. Maeguchi, A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology IEEE Journal of Solid-state Circuits. ,vol. 26, pp. 600- 606 ,(1991) , 10.1109/4.75061
Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, Digital Integrated Circuits ,(1995)