Design and Analysis of Approximate Compressors for Multiplication

摘要: Inexact (or approximate) computing is an attractive paradigm for digital processing at nanometric scales. particularly interesting computer arithmetic designs. This paper deals with the analysis and design of two new approximate 4-2 compressors utilization in a multiplier. These designs rely on different features compression, such that imprecision computation (as measured by error rate so-called normalized distance) can meet respect to circuit-based figures merit (number transistors, delay power consumption). Four schemes utilizing proposed are analyzed Dadda Extensive simulation results provided application multipliers image presented. The show accomplish significant reductions dissipation, transistor count compared exact design; moreover, multiplier provide excellent capabilities multiplication average distance peak signal-to-noise ratio (more than 50 dB considered examples).