Low power CMOS pass logic 4-2 compressor for high-speed multiplication
作者： D. Radhakrishnan , A.P. Preethy
DOI: 10.1109/MWSCAS.2000.951453
关键词:
摘要: A novel CMOS 4-2 compressor using pass logic is presented in this paper. An XOR-XNOR combination gate used to build the circuit while totally eliminating use of inverters. The total power dissipation has been cut down a minimum providing full output voltage swing at all nodes circuit. Furthermore, complete implemented with bare 28 transistors.
sci-hub.se 参考文章(15)
Yasuaki Iwase, Youji Kanie, Yasushi Kubota, Shuhei Tsuchimoto, Shinji Toyoyama, 4-2 Compressor with Complementary Pass-Transistor Logic IEICE Transactions on Electronics. ,vol. 77, pp. 647- 649 ,(1994)
N. Ohkubo, M. Suzuki, T. Shinbo, T. Yamanaka, A. Shimizu, K. Sasaki, Y. Nakagome, A 4.4 ns CMOS 54/spl times/54-b multiplier using pass-transistor multiplexer IEEE Journal of Solid-state Circuits. ,vol. 30, pp. 251- 257 ,(1995) , 10.1109/4.364439
C. S. Wallace, A Suggestion for a Fast Multiplier IEEE Transactions on Electronic Computers. ,vol. 13, pp. 14- 17 ,(1964) , 10.1109/PGEC.1964.263830
Shen-Fu Hsiao, Ming-Roun Jiang, Jia-Sien Yeh, Design of high-speed low-power 3-2 counter and 4-2 compressor for fast multipliers Electronics Letters. ,vol. 34, pp. 341- 343 ,(1998) , 10.1049/EL:19980306
D. Radhakrishnan, Design of CMOS circuits IEE Proceedings G Circuits, Devices and Systems. ,vol. 138, pp. 83- 90 ,(1991) , 10.1049/IP-G-2.1991.0016
D. Radhakrishnan, S.R. Whitaker, G.K. Maki, Formal design procedures for pass transistor switching circuits IEEE Journal of Solid-state Circuits. ,vol. 20, pp. 531- 536 ,(1985) , 10.1109/JSSC.1985.1052339
M. Margala, N.G. Durdle, Low-power low-voltage 4-2 compressors for VLSI applications Proceedings IEEE Alessandro Volta Memorial Workshop on Low-Power Design. pp. 84- 90 ,(1999) , 10.1109/LPD.1999.750407
M. Nagamatsu, S. Tanaka, J. Mori, K. Hirano, T. Noguchi, K. Hatanaka, A 15-ns 32*32-b CMOS multiplier with an improved parallel structure IEEE Journal of Solid-state Circuits. ,vol. 25, pp. 494- 497 ,(1990) , 10.1109/4.52175
G.M. Blair, Designing low-power digital CMOS Electronics & Communication Engineering Journal. ,vol. 6, pp. 229- 236 ,(1994) , 10.1049/ECEJ:19940505
D. Ghosh, S.K. Nandy, K. Parthasarathy, TWTXBB: a low latency, high throughput multiplier architecture using a new 4/spl rarr/2 compressor international conference on vlsi design. pp. 77- 82 ,(1994) , 10.1109/ICVD.1994.282660