IMPACT: imprecise adders for low-power approximate computing

摘要: Low-power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most applications, the final output interpreted by human senses, which are not perfect. This fact obviates need to produce exactly correct numerical outputs. Previous research in this context exploits error-resiliency primarily through voltage over-scaling, utilizing algorithmic architectural techniques mitigate resulting errors. paper, we propose logic complexity reduction as alternative approach take advantage of relaxation accuracy. We demonstrate concept proposing imprecise or approximate Full Adder (FA) cells with reduced at transistor level, utilize them design multi-bit adders. addition inherent switched capacitance, our result significantly shorter critical paths, enabling scaling. architectures video image compression using proposed arithmetic units, evaluate efficacy approach. Post-layout simulations indicate power savings up 60% area 37% insignificant loss quality, when compared existing implementations.