Approximate adder synthesis for area- and energy-efficient FIR filters in CMOS VLSI

摘要: This paper proposes the synthesis of approximate adders to improve area and energy efficiency FIR filters implemented in CMOS. We demonstrate per sample savings hardware reduction with our design method. All are addition improvements obtained on previously optimized digital which state-of-the-art multiplierless multiple constant multiplication optimizations included Digital finite impulse response largely used multimedia systems can tolerate levels approximations computing or loss accuracy arithmetic dataflow. Our work deals different approximation ripple-carry part hardware, fully synthesized CMOS, later compared best precise implementation same filter. results show that effort explore low power circuits through approach is validated reductions up 18.8% 15.5% respectively, without compromising frequency Signal Noise Ratio (SNR) recorded 16-bit audio signals. adder method enables a higher degree efficiencies CMOS VLSI filters.