Hybrid approximate multiplier architectures for improved power-accuracy trade-offs

摘要: Approximate computing forms a promising design alternative for inherently error resilient applications, trading accuracy power savings. In this paper, we exploit multi-level approximation, i.e. at the algorithmic, logic and circuit level, to low approximate arithmetic architectures hardware multipliers. Motivated from limited savings that approximation techniques can achieve in isolation, explore hybrid methods apply simultaneously more than one different layers. We introduce concept of perforation newly defined space designs showing it leads lower consumption every examined range. To address increased complexity target space, an heuristic optimization technique corresponding framework automatically generates low-power multipliers requiring small number evaluations, synthesis, simulation, timing analysis. Through extensive experimentation, show proposed converge towards optimal solutions deliver are always efficient with respect state-of-art approaches. Power 11% reported bounds 30% case relaxed constraints.