FPGA implementation of high speed multiplier using higher order compressors
作者： P.S. Marimuthu , R. , Balamurugan , S. , Tirumala
DOI: 10.1109/ICRCC.2012.6450579
关键词:
摘要: In general applications such as image processing signal and many similar find most of the work is done through multipliers to execute complex instructions. We generally use low order compressors for this multiplication operations. proposed paper, we are using higher operation. As these have less delay, power consumption but also occupies slightly larger area helps in incrementing execution speed whole multiplier.
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