Digital low pass filter for digital signals and method for processing a digital signal

摘要: The low-pass filter has a flank detector (ED) coupled at its input to an terminal receiving signal (IN) with 2 possible levels and output the reset (Rst) of clock counter (BC). outputs are state memory (FSM), providing (OUT) switched each time reaches given count. period duration (clk) is least 10 imes smaller than minimum pulse useful signal, count variable set start value by before increasing or reducing via pulses.