作者: Yun Yin , Baoyong Chi , Yanqiang Gao , Xiaodong Liu , Zhihua Wang
DOI: 10.1109/TCSI.2014.2334851
关键词: Engineering 、 CMOS 、 Image response 、 Amplifier 、 Frequency synthesizer 、 Phase-locked loop 、 Electronic engineering 、 Baseband 、 Wideband 、 Transmitter 、 Electrical engineering
摘要: A 0.1-5.0 GHz 65 nm CMOS reconfigurable transmitter for private network wireless communications is presented. The integrates a 0.1-1.5 high-efficiency dual-mode power amplifier to support low-cost narrowband applications and 0.45-5.0 efficiency-optimized pre-power high-performance wideband applications. PLL frequency synthesizer, DACs with sampling rate the digital baseband processing standard JESD207 interface are all included implement highly-integrated transmitter. Specifically, proposed digitally-assisted self-calibration technique LO leakage image rejection, achieves 52 dBc >53 rejection ratio (IRR), showing 20 dB 30 improvement compared un-calibrated cases, respectively. system verifications have demonstrated an EVM of 1.7% 905 MHz EDGE 19.5 dBm output power, 3.2% LTE Band42 5.5 power. This has achieved comparable or even better performance in linearity, noise floor consumption state-of-the-art transmitters.