System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown
作者： Taizhi Liu , Chang-Chih Chen , Soonyoung Cha , Linda Milor
DOI: 10.1016/J.MICROREL.2015.06.008
关键词: Degradation (telecommunications) 、 Simulation 、 Reliability (semiconductor) 、 System level 、 Temperature instability 、 Oxide 、 AND gate 、 Engineering 、 Hot-carrier injection 、 Work (thermodynamics) 、 Electronic engineering
摘要: Abstract A framework is proposed to analyze system-level reliability and evaluate the lifetimes of state-of-art microprocessors considering impact process–voltage–temperature (PVT) variations device wearout mechanisms, including bias temperature instability (BTI), hot carrier injection (HCI), gate oxide breakdown (GOBD). This work studies not only system performance degradation due each mechanism individually, but also while all these mechanisms happen simultaneously. unified gate-delay model developed combine PVT aging effect, then a statistical timing engine constructed degradations lifetimes.
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