Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing
作者： Dana Lee , Yuniarto Widjaja , John W. Cooksey , Changyuan Chen , Feng Gao
DOI:
关键词: Reading (computer) 、 Materials science 、 Communication channel 、 Substrate (electronics) 、 Optoelectronics 、 NAND gate 、 Nand flash memory 、 Electrical engineering
摘要: A split gate NAND flash memory structure is formed on a semiconductor substrate of first conductivity type. The comprises region second type in the with substrate, spaced apart from region. continuous channel defined between and plurality floating gates are one another each positioned over separate portion control provided associated adjacent to gate. Each has two portions: capacitively coupled thereto.
google.de 参考文章(33)
Isao Nojima, Hieu Van Tran, Amitay Levi, Hung Q. Nguyen, Seek window verify program system and method for a multilevel non-volatile memory integrated circuit system ,(2003)
Tomoko Ogura, Tomoya Saito, Seiki Ogura, Kimihiro Satoh, Twin NAND device structure, array operations and fabrication method ,(2003)
Masataka Kato, Shiro Akamatsu, Fukuo Owada, Masahito Takahashi, Akihiko Satoh, Semiconductor integrated circuit device and a method of manufacturing thereof ,(2001)
James A. Cunningham, Richard A. Blanchard, Method and apparatus for providing an embedded flash-EEPROM technology ,(2000)
Cheng-Yuan Hsu, Chi-Wei Hung, Da Sung, Chi-Shan Wu, S.C. Chen, H.H. Kuo, J.Y. Pan, C.L. Chen, I.C. Chuang, V. Huang, C.C. Hsue, D.-T. Fan, Jung-Chang Lu, C.Y.-S. Cho, K. Tseng, A. Hsu, B. Sheen, P. Tuntasood, Chiou-Feng Chen, Split-gate NAND flash memory at 120nm technology node featuring fast programming and erase symposium on vlsi technology. pp. 78- 79 ,(2004) , 10.1109/VLSIT.2004.1345403
Ping Wang, Bing Yeh, A single transistor non-volatile electrically alterable semiconductor memory device ,(1992)
Fujio C O Patent Division Masuoka, Programmable semiconductor memory ,(1988)
Leonard Forbes, Jerome M. Eldridge, Kie Y. Ahn, Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers ,(2006)
Eliyahou Harari, Jack H. Yuan, Daniel C. Guterman, George Samachisa, Dual floating gate EEPROM cell array with steering gates shared by adjacent cells ,(1999)
Kuo-Chi Tu, Non-volatile memory technology compatible with 1T-RAM process ,(2003)