Distributed arithmetic realisation of cyclic convolution and its DFT application

摘要: The authors present a new hardware-efficient group distributed arithmetic (GDA) design approach for the one-dimensional (1-D) discrete Fourier transform (DFT). adopts (DA) computation and exploits good features of cyclic convolution to facilitate an efficient realisation 1-D N-point DFT using small ROM modules, barrel shifter, N accumulators. proposed GDA is achieved by rearranging contents into several groups such that all elements in can be accessed simultaneously accumulating outputs increase utilisation. Moreover, combining symmetrical property coefficients with requires only half stored, which further reduces size factor two. Realisation long-length formulated based on data permutation rows columns matrix directly partition short ones, so length DFTs may realised efficiently achieve low hardware cost. This termed ‘block-based approach’. Compared existing systolic array designs DA-based designs, reduce delay–area product 29%–68% 0.35 μm CMOS cell library.