Way prediction unit and a method for operating the same
作者： Thang M. Tran , James K. Pickett
DOI:
关键词: Computer hardware 、 Parallel computing 、 Superscalar microprocessor 、 Unit (housing) 、 Pipeline transport 、 Fetch 、 Limiting 、 Cycles per instruction 、 Computer science 、 Cache
摘要: A way prediction unit for a superscalar microprocessor is provided which predicts the next fetch address as well of instruction cache that current hits in while instructions associated with are being read from cache. The intended high frequency microprocessors associative caches tend to be clock cycle limiting, causing mechanism require more than one between requests. Therefore, an can made every using predicted until incorrect or predicted. processing pipelines each cycle.
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