Interconnection of autonomous error-tolerant cells

摘要: In this paper we propose an interconnection scheme for the autonomous error-tolerant (AET) cell introduced in a by Valtonen et al. (2001). The objective here is to partition system into identical, physically and highly configurable cells that can operate without outside control or synchronization. billion transistor Network-on-Chip (NoC) circuits, AET fabric could prove flexible reliable, allow low replication costs, due homogeneousity. However, many challenges persist before useful be constructed: need (i) scalable long-distance communication-global bus wiring fits poorly homogeneous, symmetric limits scalability, (ii) communication-cells all directions, within given range, should accessible (iii) self-synchronizing topologies, absence of external synchronization; (iv) interconnect implemented using near-future technology generations, (v) efficient when constituting billions cells.