A method for manufacturing a gate array integrated circuit device
作者： Samuel Chih , Osam c
DOI:
关键词: Function (engineering) 、 Engineering 、 Integrated circuit 、 SIMPLE (military communications protocol) 、 Electronic engineering 、 Symbol (formal) 、 Gate array 、 Systems design 、 Macro 、 Computer hardware 、 Engineering design process
摘要: A method for manufacturing a gate array IC device in which the turn-around time of design is short, system simple, and fast-access memory capacity required process reduced. The includes master bulk pattern basic cell on semiconductor substrate, storing, semi-permanent memory, symbol data detailed standard macro cells expandes prior to designing logic system. Each comprises one or more has function. expanded plural complicated sophisticated function than cells. In addition, functions are technology area. When designer creates system, only (DO, EO,...) (500) connections thereof (111, 112,...) used stored so that it relatively easy Actual conductive wiring patterns synthesized from data; these produced substrate already provided with as connect accordance design.
google.co.in 参考文章(6)
Yuichi Teranishi, Masayoshi Abe, LSI layout and method for fabrication of the same ,(1976)
Rokutaro Ogawa, Tohru Hosomizu, Kenichi Ohno, Mitsuhisa Shimizu, Large scale semiconductor integrated circuit device ,(1978)
Wesley C. Finger, Gerald B. Long, Macro assembler process for automated circuit design ,(1980)
Nobuaki Kawato, Takao Saito, Takao Uehara, A CAD System for Logic Design Based on Frames and Demons design automation conference. pp. 451- 456 ,(1981) , 10.5555/800073.802342
T. Sudo, T. Ohtsuki, S. Goto, CAD systems for VLSI in Japan Proceedings of the IEEE. ,vol. 71, pp. 129- 143 ,(1983) , 10.1109/PROC.1983.12534
Eugene Shapiro, Ravindra K. Nair, Se J. Hong, High speed machine for the physical design of very large scale integrated circuits ,(1981)