Design and Simulation of the Aquarius-II Multiprocessor
作者： Vason P. Srini , Tam M. Nguyen , Darren R. Busing , Mike J. Carlton , Bruce K. Holmer
关键词: Distributed shared memory 、 Parallel computing 、 Shared memory 、 Computer science 、 Cache-only memory architecture 、 Interleaved memory 、 Memory map 、 Registered memory 、 Uniform memory access 、 Distributed memory
摘要: Aquarius-II is a cache coherent multiprocessor system designed for the parallel execution of Prolog programs. It contains two tiers memory: synchronization memory and high bandwidth (HB) memory. The consists snooping caches connected to bus used store rendezvous points, bits, variables such as locks semaphores most write shared data. HB bulk application program code an inexpensive VLSI chip based crossbar interconnection network do not have full capability. architecture evaluated by simulation programs on Aquarius-II. design details components results are presented. Simulation indicate that tier significantly reduces interference speeds up when compared single multi. This multiprocesor has potential support other programming paradigms.
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