Dynamic random access memory cell and array having vertical channel transistor
作者： Hui-Huang Chen , Chih-Yuan Chen , Chun-Cheng Chen , Sheng-Fu Yang
DOI:
关键词: Dynamic random-access memory 、 Capacitor 、 Transistor 、 Gate oxide 、 Drain-induced barrier lowering 、 Electrical engineering 、 Gate dielectric 、 Optoelectronics 、 Layer (electronics) 、 Semiconductor 、 Materials science
摘要: A dynamic random access memory cell having vertical channel transistor includes a semiconductor pillar, drain layer, an assisted gate, control source and capacitor. The has active region formed by the pillar. layer is at bottom of gate beside separated from first dielectric layer. second top capacitor to electrical connect
google.co.uk 参考文章(41)
Larson D. Lindholm, David K. Hwang, Methods of forming vertical field effect transistors, vertical field effect transistors, and dram cells ,(2008)
Kazuo Nakazato, Teruaki Kisu, Masahito Takahashi, Method of manufacturing semiconductor memory device and semiconductor memory device ,(2002)
Jong-ho Lee, Pillar-type field effect transistor having low leakage current ,(2011)
Jong-Chul Park, Yun-Seung Kang, Method of fabricating semiconductor device having metal-semiconductor compound regions ,(2010)
Eric Carman, Vertical Transistor Memory Cell and Array ,(2009)
Leonard Forbes, Vertical transistor, memory cell, device, system and method of forming same ,(2005)
Hyoung-sub Kim, Semiconductor device having vertical conduction transistors and cylindrical cell gates ,(1994)
Brian S. Lee, Till Schlösser, DRAM cell arrangement with vertical MOS transistors, and method for its fabrication ,(2003)
Robert J. Burke, Anand Srinivasan, Sanh D. Tang, Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array ,(2006)