作者: Rakesh Verma , Neeta Pandey , Rajeshwari Pandey
DOI: 10.1007/S10470-018-1315-1
关键词: CMOS 、 Functional verification 、 Electronic circuit 、 Filter (video) 、 Spice 、 Capacitor 、 Electrical impedance 、 Analog multiplier 、 Computer science 、 Electronic engineering
摘要: This paper presents higher order fractional element using the concept of impedance inverter circuit based on operational transcoductance amplifier (OTA). Firstly OTA is generalized in domain which followed by presentation novel inverted multiplier (IIMC) and its generalization. Effect parasites performance proposed IIMC also presented. The usefulness proposal illustrated through implementation filter IIMC. functional verification all circuits done SPICE simulations 0.18 µm TSMC CMOS technology parameter. capacitors orders 0.2 0.5 are realized truncated infinite domino RC ladder network considered for this work. experimentally verified hardware prototyping LM 13600N dual OTAs IC. simulation experimental results corroborate with theoretical prepositions.