作者: J.D.H. Alexander
DOI: 10.1049/EL:19750415
关键词: Synchronization 、 Pulse generator 、 Logic gate 、 Synchronous circuit 、 Clock domain crossing 、 Clock angle problem 、 Clock signal 、 Clock skew 、 Asynchronous circuit 、 Static timing analysis 、 Asynchronous system 、 Binary signal 、 Clock recovery 、 Vector clock 、 Digital clock manager 、 Clock gating 、 Timing failure 、 Electronic engineering 、 Computer science 、 Clock drift
摘要: A circuit for detecting timing errors between a binary signal and local clock pulse generator is described. Three samples are compared logical control signals the derived.