14–bit, 2.2MS/s sigma delta ADCs
作者： J. Morizio , C. Geddie , M. Nakaya , H. Noda , T. Kumamoto
DOI:
关键词: Electronic engineering 、 Design objective 、 Engineering 、 Error detection and correction 、 Delta modulation 、 Dissipation 、 Quantization (signal processing) 、 CMOS 、 Noise shaping 、 Delta-sigma modulation
摘要: This paper presents the design and test results of a 4th 6th order, 14-bit, 2.2MS/s sigma-delta ADC. The analog modulator digital decimator sections were implemented in .35µM CMOS, double poly, triple level metal 3.3v process. objectives for these ADCs was to achieve 85dB SNDR with less than 200mW power dissipation.
参考文章(8)
Gabor C. Temes, James C. Candy, Oversampling Delta Sigma Data Converters ,(1991)
Gabor C. Temes, Steven R. Norsworthy, Richard Schreier, Ieee Circuits, Delta-sigma data converters : theory, design, and simulation IEEE Press. ,(1997)
C.S.G. Conroy, W.A. Lane, M.A. Moran, Statistical design techniques for D/A converters IEEE Journal of Solid-state Circuits. ,vol. 24, pp. 1118- 1128 ,(1989) , 10.1109/4.34100
J. Candy, A Use of Double Integration in Sigma Delta Modulation IEEE Transactions on Communications. ,vol. 33, pp. 249- 258 ,(1985) , 10.1109/TCOM.1985.1096276
M.J. McNutt, S. LeMarquis, J.L. Dunkley, Systematic capacitance matching errors and corrective layout procedures IEEE Journal of Solid-state Circuits. ,vol. 29, pp. 611- 616 ,(1994) , 10.1109/4.284714
Kwang Young Kim, N. Kusayanagi, A.A. Abidi, A 10-b, 100-MS/s CMOS A/D converter IEEE Journal of Solid-state Circuits. ,vol. 32, pp. 302- 311 ,(1997) , 10.1109/4.557627
T.C. Leslie, B. Singh, An improved sigma-delta modulator architecture international symposium on circuits and systems. pp. 372- 375 ,(1990) , 10.1109/ISCAS.1990.112045
B.E. Boser, B.A. Wooley, The design of sigma-delta modulation analog-to-digital converters IEEE Journal of Solid-state Circuits. ,vol. 23, pp. 1298- 1308 ,(1988) , 10.1109/4.90025