High-Performance On-Chip Low-Pass Filters Using CPW and Slow-Wave-CPW Transmission Lines on Porous Silicon

摘要: We report on the design, fabrication, and characterization of high-performance stepped-impedance filters (SIFs) a locally formed porous Si layer CMOS wafer. This technology provides appropriate platform to reduce high losses within substrate, along with possibility tune substrate permittivity in order achieve characteristic impedance ( $Z_{C}$ ) transmission lines, which are important for specific other passive circuits, e.g., power dividers. By combining high- coplanar waveguides (CPWs) low- slow-wave CPWs (S-CPWs), high-quality SIFs were achieved, cutoff frequencies at 30 60 GHz. These characterized frequency range 0–100 GHz demonstrated an insertion loss lower than 2 dB whole passband rejection higher stopband. The achieved performance is better that exhibited by using only S-CPWs.