作者: Robert E. Dietterle , David A. Rowe , Binneg Y. Lao
DOI:
关键词: Signal 、 Electrical engineering 、 Chip carrier 、 Printed circuit board 、 Materials science 、 Ground plane 、 Layer (electronics) 、 Line (electrical engineering) 、 Redistribution layer 、 Electrical conductor 、 Optoelectronics
摘要: A multilayered integrated circuit chip carrier has a top layer, signal line ground power conductor and bottom layer with separating between adjacent layers. Each coplanar conductive dielectric portions, the layers being primarily dielectric. The supports an launcher pads on couple lines of printed board to spaced points about periphery substantially constant impedance is achieved. separated from by plane layer. Conductive via through are placed in form plurality separate paths each Via also break up cavities thus increase cavity resonance above frequencies provide isolation. Thermal columns portions other under cooling. Large grounded areas reduce unwanted coupling external environment. capacitive provides