System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding
作者： Ralph James
DOI:
关键词: Address bus 、 Clock generator 、 Controller (computing) 、 Real-time computing 、 Downstream (networking) 、 Control bus 、 Computer science 、 Computer hardware 、 Bus network 、 Transmitter 、 System bus
摘要: A memory system includes a hub controller that sends write data to plurality of modules through downstream bus and receives read from the an upstream bus. The receiver coupled transmitter Similarly, each Each receive clock generator is synchronized by coupling known pattern receiver. determines which phase best captures uses during normal operation.
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