Testing for tunneling opens
作者： J.C.M. Li , E.J. McCluskey
关键词: Quantum tunnelling 、 Low voltage 、 Logic testing 、 Topology 、 Electronic circuit 、 Boolean function 、 Combinational logic 、 Engineering 、 Failure mode and effects analysis 、 Electronic engineering
摘要: A tunneling-open failure mode is proposed and carefully studied. circuit with a tunneling open could pass at-speed Boolean tests but fail VLV testing or I/sub DDQ/ testing. Theoretical calculations as well experiments confirm the existence of opens. The Murphy experimental data show that seven out nine VLV-only circuits can be explained by this mode. All these survived 366 hours temperature burn-in. Finally, cost effective screening strategy proposed.
computer.org
sci-hub.se 参考文章(51)
Jon G. Kuhl, Sudhakar M. Reddy, On Testable Design for CMOS Logic Circuits. international test conference. pp. 435- 445 ,(1983)
Gabriel M. Silberman, Zeev Barzilai, Barry K. Rosen, J. Lawrence Carter, Vijay S. Iyengar, Joe D. Rutledge, Indira Nair, Efficient Fault Simulation of CMOS Circuits with Accurate Models. international test conference. pp. 520- 529 ,(1986)
Richard H. Wilcox, William C. Mann, Redundancy techniques for computing systems Spartan Books. ,(1962)
M. R. Taylor, E. I. Cole, C. L. Henderson, A. N. Campbell, Case history: Failure analysis of a CMOS SRAM with an intermittent open contact tfa. pp. 11- 15 ,(1991)
IDDQ testing of VLSI circuits Kluwer Academic Publishers. ,(1993) , 10.1007/978-1-4615-3146-3
Yusuf Leblebici, Sung-Mo Kang, Hot-carrier reliability of MOS VLSI circuits ,(1993)
J.C.M. Li, Chao-Wen Tseng, E.J. McCluskey, Testing for resistive opens and stuck opens international test conference. pp. 1049- 1058 ,(2001) , 10.1109/TEST.2001.966731
S. Johnson, Residual charge on the faulty floating gate CMOS transistor international test conference. pp. 555- 561 ,(1994) , 10.1109/TEST.1994.527999
P. Nigh, D. Forlenza, F. Motika, Application and analysis of IDDQ diagnostic software international test conference. pp. 319- 327 ,(1997) , 10.1109/TEST.1997.639633
K.F. Schuegraf, C.C. King, C. Hu, Ultra-thin silicon dioxide leakage current and scaling limit symposium on vlsi technology. pp. 18- 19 ,(1992) , 10.1109/VLSIT.1992.200622