Chip yield for FETs fabricated on low-surface-defect GaAs wafers grown by a new MBE system

摘要: Abstract A very low defect density is achieved with a new MBE system, in which the diameter of top-heated Ga cell as big 60 mm and distance between wafer optimized at 450 by simulation. This system grows GaAs wafers 14.6 cm−2 for defects larger than 0.67 μm2. Our chip yield estimation field effect transistors LSIs fabricated on shows that grown can integrate 100 000 FETs if each FET gate 0.3 μm long 5 wide 42% assumed.