作者: S. Li , K. Zhang , J.-C. Lo
DOI: 10.1109/DFTVS.2000.887178
关键词: Electronic engineering 、 Order (group theory) 、 Test data 、 Very-large-scale integration 、 Algorithm 、 Engineering 、 CMOS 、 Signature (logic)
摘要: The proposed 2/sup nd/ order current signature technique considers both the 1/sup st/ mean and variance information to provide a more robust effective means of die selection. We examined I/sub DDQ/ testing data from SEMATECH by compared results those traditional single threshold delta techniques. found that analysis may enable way implement testing. In particular, clear distinction can be made between defected defect-free dies. dies identified delta-I/sub are quite similar for data. However, future deep sub-micron VLSI where value vary significantly, has definite advantage being robust.