Asynchronous glitchless digital MUX
作者： Richard R. Rasmussen
DOI:
关键词: Glitch 、 Electronic engineering 、 Pulse-width modulation 、 Signal 、 Asynchronous communication 、 Synchronization 、 Computer science 、 Clock signal 、 State (computer science) 、 Multiplexer
摘要: Circuit and method of glitchless switching between asynchronous data inputs to a digital multiplexer (MUX) by maintaining conditioning the width clock pulse corresponding first input signal so that an output is produced having never narrower than narrowest signals, i.e., does not produce narrow-pulse glitch. The circuit comprises select in parallel both MUX via latch device edge detector triggering synchronization assembly. assembly freezes last state received from multiplexer. original D0 at high until new D1 cleared through
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