FPGA based DSC-PLL for grid harmonics and voltage unbalance effect elimination

摘要: In this paper, the design of DSC-PLL (Delayed Signal Cancellation Phase Locked Loop) based on FPGA is discussed. This method shows outstanding performance for detection fundamental positive sequence component voltage when grid polluted by harmonics and unbalance. The harmonic elimination technique DSC analyzed implemented with a discrete fixed point based. Process investigated designed system generator compatible MATLAB/SIMULINK, which schematic directly converted to HDL (Hardware Descriptions Language) then programmed into FPGA. To verify conventional SRF-PLL, two methods are XC7Z030 tested under distorted three-phase conditions respectively. results show SRF-PLL contains continuous oscillations influence, but proposed perfectly eliminates any within maximum 5.44ms detects successfully voltage.