Grid Synchronization PLL Based on Cascaded Delayed Signal Cancellation

摘要: During the grid synchronization of distributed generation (DG) units, phase-locked loop (PLL) is well accepted as an efficient approach to detect phase angle. Conventional PLL schemes used in DG controller have compromise between steady-state accuracy and transient dynamics when voltage polluted by unbalance harmonics. To simultaneously realize good performances, this paper proposes a general delayed signal cancellation (DSC) operator, which can be tailored eliminate any specified harmonic. The proposed DSC operator further cascaded stepwise reject all undesired Then conditioned achieve fast response at high control bandwidth without suffering from error caused Based on differently configured operators, two designs are then developed, namely CDSC-PLL1 CDSC-PLL2. Specifically, aimed for with odd/even harmonics, while CDSC-PLL2 addresses asymmetrical i.e., harmonics arising asymmetrically distorted three-phase voltages. By introducing frequency feedback loop, operate properly during considerable variations, even jump or severe also present. All very simple structure easily implemented. superior performance confirmed experimental results.