作者: Garrett M. Drapala , Michael Fee , Deanna P. Dunn
DOI:
关键词: Real-time computing 、 Computer hardware 、 System bus 、 Dynamic data 、 Bandwidth (computing) 、 Local bus 、 Computer science 、 Control bus 、 Interface (computing) 、 Transfer (computing) 、 Pipeline (computing)
摘要: As a performance critical (high or full speed) request for computer system data bus travels down central pipeline, the detects whether interface is currently empty there an ongoing half-speed transfer. If low speed transfer, dynamically time shift slows read rate out of interleave buffer to half speed, and utilizes free bandwidth. This dynamic “zippering” shifting prevents pipe pass from being rejected because whole unavailable.