Analyzing the Hardware Costs of Different Security-Layer Variants for a Low-Cost RFID Tag

摘要: Radio-frequency identification (RFID) technology is the enabler for future Internet of Things (IoT) where security will play an important role. In this work, we evaluate costs adding different security-layer variants that are based on symmetric cryptography to a low-cost RFID tag. contrast related do not only consider cryptographic-algorithm implementation, but also relate protocol handling layer. Further show using tag architecture low-resource 8-bit microcontroller highly advantageous. Such approach flexibility allows combining implementation and cryptographic algorithm microcontroller. Expensive resources like memory can be easily reused, lowering overall hardware costs. We have synthesized security-enabled 130 nm CMOS technology, algorithms AES NOEKEON demonstrate effectiveness our approach. Average power consumption 2 μ W at clock frequency 106 kHz. Hardware range from about 1100 GEs 4500 AES.