作者: W.E. Lee , W.F. Guthrie , M.W. Cresswell , R.A. Allen , J.J. Sniegowski
DOI: 10.1109/ICMTS.1997.589322
关键词: Metrology 、 Monocrystalline silicon 、 Optics 、 Lattice (order) 、 Laser linewidth 、 Voltage 、 Thin film 、 Silicon 、 Lithography 、 Materials science
摘要: Electrical test structures replicated in thin films of mono-crystalline silicon offer potential benefits as physical standards for linewidth and overlay metrology. When the structure's features, lattice monocrystalline film, surface plane film have particular mutual orientations, junctions Kelvin voltage taps with bridge feature structure three-dimensional geometries which can be specified by four well-defined dimensional parameters. Since voltage-tap linewidths determine magnitude voltage-tap-induced electrical bridge-length-shortening effect, measurement latter offers an additional means validating measurements feature. This paper reports results simulations current-flow through voltage-tap-to-bridge junctions, thus providing values expected effect a application. In addition, calculated are compared experimental measurements. A parametric representation effective function has been developed. Its purpose is to facilitate rapid independent estimation shortening generated during performed on silicon.