Multiple select gate architecture
作者： Seiichi Aritome
DOI:
关键词: Footprint (electronics) 、 Electronic engineering 、 Architecture 、 Engineering 、 Sizing 、 Feature (computer vision) 、 Bit line 、 Computer hardware
摘要: Non-volatile memory devices including multiple series-coupled select gates on the drain and/or source ends of strings non-volatile cells. By utilizing gates, each gate can be made using smaller features sizes while achieving same level protection against GIDL and other forms current leakage. reducing feature size footprint cells reduced, thereby facilitating device sizing. Further reductions in sizing may achieved a staggered self-aligned bit line contact configuration.
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