Design of sampled analog wavelet processor architecture for cochlear implant application
作者： Piyush M. Chaniyara , Prabhat Kumar Srivastava , B. Suresha , A. Subhakumar Reddy
DOI: 10.1007/S10470-015-0642-8
关键词: Wavelet 、 Quantization (signal processing) 、 Signal 、 Haar wavelet 、 Microarchitecture 、 CMOS 、 Electronic engineering 、 Switched capacitor 、 Operational amplifier 、 Computer science
摘要: This paper presents the design of sampled analog wavelet processor architecture for cochlear implant application using discrete Haar transform. Basic element is operational amplifier based switched capacitor integrator circuit. distributes input signal frequencies into different predefined frequency band and on sensitivity region by arbitrary tree structure. The presented beneficial in terms processing time signal, area complexity avoiding quantization encoding process part data converter circuits. Simulation results this carried out with CMOS 90 nm technology.
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Robert V. Shannon, Qian-Jie Fu, John Galvin, Lendra Friesen, Speech Perception with Cochlear Implants Springer New York. pp. 334- 376 ,(2004) , 10.1007/978-0-387-22585-2_8
Mal, Dhar, Analog sampled data architecture for discrete cosine transform international conference on asic. pp. 502- 505 ,(2003) , 10.1109/ICASIC.2003.1277596
C. Abel, J. Park, M. Ismail, B. Lohiser, S. Justice, S. Bibyk, T. Fiez, A switched-current silicon cochlea world congress on computational intelligence. ,vol. 3, pp. 1842- 1847 ,(1994) , 10.1109/ICNN.1994.374438
A.K. Mal, A. Basu, A.S. Dhar, Sampled analog architecture for DCT and DST international symposium on circuits and systems. ,vol. 2, pp. 825- 828 ,(2004) , 10.1109/ISCAS.2004.1329399
Fathi Kallel, Rafael Laboissiere, Ahmed Ben Hamida, Christian Berger-Vachon, Influence of a shift in frequency distribution and analysis rate on phoneme intelligibility in noisy environments for simulated bilateral cochlear implants Applied Acoustics. ,vol. 74, pp. 10- 17 ,(2013) , 10.1016/J.APACOUST.2012.05.014
Anand Darji, Shubham Agrawal, Ankit Oza, Vipul Sinha, Aditya Verma, SN Merchant, Arun N Chandorkar, None, Dual-Scan Parallel Flipping Architecture for a Lifting-Based 2-D Discrete Wavelet Transform IEEE Transactions on Circuits and Systems Ii-express Briefs. ,vol. 61, pp. 433- 437 ,(2014) , 10.1109/TCSII.2014.2319975
Xiaodong Wu, Yongming Li, Hongyi Chen, Programmable wavelet packet transform processor Electronics Letters. ,vol. 35, pp. 449- 450 ,(1999) , 10.1049/EL:19990330
Ahmed K Al-Sulaifanie, Arash Ahmadi, Mark Zwolinski, None, Very Large Scale Integration Architecture for Integer Wavelet Transform Iet Computers and Digital Techniques. ,vol. 4, pp. 471- 483 ,(2010) , 10.1049/IET-CDT.2009.0021
Domingo Garcia, Mohamed Mansour, Murtaza Ali, A Flexible Hardware Architecture for Wavelet Packet Transform With Arbitrary Tree Structure IEEE Transactions on Circuits and Systems Ii-express Briefs. ,vol. 60, pp. 657- 661 ,(2013) , 10.1109/TCSII.2013.2277964
C. Desmouliers, E. Oruklu, J. Saniie, Discrete wavelet transform realisation using run-time reconfiguration of field programmable gate array (FPGA)s Iet Circuits Devices & Systems. ,vol. 5, pp. 321- 328 ,(2011) , 10.1049/IET-CDS.2010.0259