Discrete wavelet transform realisation using run-time reconfiguration of field programmable gate array (FPGA)s

摘要: Designing a universal embedded hardware architecture for discrete wavelet transform is challenging problem because of the diversity among kernel filters. In this work, authors present three different architectures implementing multiple kernels. The first scheme utilises fixed, parallel all required kernels, whereas second employs processing element (PE)-based datapath that can be configured filters during run-time. third makes use partial run-time configuration FPGA units dynamically programming any desired filter. As case study, synthesis results simultaneous implementation six wavelets proposed methods. Performance analysis and comparison area, timing power are presented Virtex-II Pro implementations.