作者: P.M. Garone , V. Venkataraman , J.C. Sturni
DOI: 10.1109/55.79566
关键词: Silicon 、 Electrical engineering 、 AND gate 、 Numerical modeling 、 Condensed matter physics 、 Capacitance 、 Materials science 、 Heterojunction 、 Charge carrier 、 Semiconductor materials 、 Electronic band structure
摘要: The confinement of carriers in a MOS-gated Ge/sub x/Si/sub 1-x/ heterostructure is numerically modeled. structure uses MOS gate to modulate the hole density at buried Si/sub x//Ge/sub x/Si//sub interface. number holes well modeled as function and bias. then confirmed by capacitance-voltage Hall measurements. Numerical modeling used predict maximum achievable interface structural design, clear experimental evidence for such carrier given. >