Hardware Architecture for Real-Time Computation of Image Component Feature Descriptors on a FPGA:

摘要: This paper describes a hardware architecture for real-time image component labeling and the computation of feature descriptors. These descriptors are object related properties used to describe each component. Embedded machine vision systems demand robust performance power efficiency as well minimum area utilization, depending on deployed application. In proposed architecture, modules calculation run in parallel. A CMOS sensor (MT9V032), operating at maximum clock frequency 27 MHz, was capture images. The synthesized implemented Xilinx Spartan-6 FPGA. developed is capable processing 390 video frames per second size 640 × 480 pixels. Dynamic consumption 13 mW 86 second.