An implantable VLSI architecture for real time spike sorting in cortically controlled Brain Machine Interfaces

摘要: Brain Machine Interface (BMI) systems demand real-time spike sorting to instantaneously decode the trains of simultaneously recorded cortical neurons. Real-time sorting, however, requires extensive computational power that is not feasible implement in implantable BMI architectures, thereby requiring transmission high-bandwidth raw neural data an external computer. In this work, we describe a miniaturized, low power, programmable hardware module capable performing task within resource constraints chip. The computes sparse representation waveforms followed by “smart” thresholding. This cascade restricts subset projections preserve discriminative features neuron-specific waveforms. addition, it further reduces telemetry bandwidth making wirelessly transmit only important biological information outside world, improving efficiency, practicality and viability clinical applications.