Heterogeneous SRAM Cell Sizing for Low-Power H.264 Applications
作者： Jinmo Kwon , Ik Joon Chang , Insoo Lee , Heemin Park , Jongsun Park
DOI: 10.1109/TCSI.2012.2185335
关键词:
摘要: In low-voltage operation, static random-access memory (SRAM) bit-cells suffer from large failure probabilities with technology scaling. With the increasing failures, conventional SRAM is still designed without considering importance differences found among data stored in bit-cells. This paper presents a heterogeneous sizing approach for embedded of H.264 video processor, where more important higher order bits are relatively larger and less smaller ones. As result, significantly decrease cells storing bits, which allows us to obtain better quality even lower voltage operation. find bit-cell sizes that achieve best under area constraint, we propose algorithm based on dynamic programming. Compared brute-force search, proposed greatly reduces computation time needed select 8 bit pixel. Experimental results show iso-area condition, array achieves significant PSNR improvements (average 4.49 dB at 900-mV operation) compared one identical cell sizing.
elsevier.com
sci-hub.se 参考文章(16)
I.J. Chang, J. Park, K. Kang, K. Roy, Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling Iet Circuits Devices & Systems. ,vol. 4, pp. 469- 478 ,(2010) , 10.1049/IET-CDS.2010.0137
E. Seevinck, F.J. List, J. Lohstroh, Static-noise margin analysis of MOS SRAM cells IEEE Journal of Solid-State Circuits. ,vol. 22, pp. 748- 754 ,(1987) , 10.1109/JSSC.1987.1052809
Leland Chang, Yutaka Nakamura, Robert K. Montoye, Jun Sawada, Andrew K. Martin, Kiyofumi Kinoshita, Fadi H. Gebara, Kanak B. Agarwal, Dhruva J. Acharyya, Wilfried Haensch, Kohji Hosokawa, Damir Jamsek, A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS 2007 IEEE Symposium on VLSI Circuits. pp. 252- 253 ,(2007) , 10.1109/VLSIC.2007.4342739
K. Takeda, H. Ikeda, Y. Hagihara, M. Nomura, H. Kobatake, Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit international solid-state circuits conference. pp. 2602- 2611 ,(2006) , 10.1109/ISSCC.2006.1696326
Shao-Yi Chien, Yu-Wen Huang, Ching-Yeh Chen, H.H. Chen, Liang-Gee Chen, Hardware architecture design of video compression for multimedia communication systems IEEE Communications Magazine. ,vol. 43, pp. 122- 131 ,(2005) , 10.1109/MCOM.2005.1497562
Ik Joon Chang, Jae-Joon Kim, Sang Phill Park, Kaushik Roy, A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS IEEE Journal of Solid-state Circuits. ,vol. 44, pp. 650- 658 ,(2009) , 10.1109/JSSC.2008.2011972
Xinghai Tang, V.K. De, J.D. Meindl, Intrinsic MOSFET parameter fluctuations due to random dopant placement IEEE Transactions on Very Large Scale Integration Systems. ,vol. 5, pp. 369- 376 ,(1997) , 10.1109/92.645063
Kanak Agarwal, Sani Nassif, The Impact of Random Device Variation on SRAM Cell Stability in Sub-90-nm CMOS Technologies IEEE Transactions on Very Large Scale Integration Systems. ,vol. 16, pp. 86- 97 ,(2008) , 10.1109/TVLSI.2007.909792
Do Anh-Tuan, Jeremy Yung Shern Low, Joshua Yung Lih Low, Zhi-Hui Kong, Xiaoliang Tan, Kiat-Seng Yeo, An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS IEEE Transactions on Circuits and Systems. ,vol. 58, pp. 1252- 1263 ,(2011) , 10.1109/TCSI.2010.2103154
S. Mukhopadhyay, H. Mahmoodi, K. Roy, Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 24, pp. 1859- 1880 ,(2005) , 10.1109/TCAD.2005.852295