作者: Jangwon Park , Jongsun Park , Swarup Bhunia
DOI: 10.1109/TCSII.2013.2291091
关键词:
摘要: Increasing process variations coupled with aggressive scaling of cell area and operating voltage in the quest higher density lower power have greatly affected reliability on-chip memory. Error correction code (ECC) has been traditionally used inside memory to provide uniform protection all bits a word. They suffer from either adequate against multibit failures or large overhead due encoding/decoding logic parity bits. To address this issue, we present variable data-length ECC (VL-ECC) for embedded devices digital signal processors, which data length can be dynamically reconfigured preferentially protect relatively more important In proposed VL-ECC, when number exceeds error capability, is reduced focus on order bit parts, thereby minimizing system quality degradation failures. When VL-ECC applied an H.264 processor, average peak signal-to-noise-ratio improvements up 5.12 dB are achieved compared conventional under supply 800 mV lower. With fast Fourier transform signal-to-quantization noise ratio improved by 5.2 dB.