Impacts of plasma process-induced damage on MOSFET parameter variability and reliability

摘要: Abstract Plasma process-Induced Damage (PID) is one of the critical issues in designing Metal–Oxide–Semiconductor Field-Effect Transistors (MOSFETs), because PID believed to enhance reliability degradation and variability. This paper presents how impacts on variability characterization by focusing two key damage creation mechanisms, i.e., Plasma-induced Physical (PPD) Charging (PCD). In PPD effects Si loss source/drain extension region latent defects MOSFET performance are discussed means range theory Technology-Computer-Aided-Design (TCAD) simulations. It presented that, under fluctuation plasma parameters, enhances threshold voltage shift (ΔVth) drain current. Regarding PCD ΔVth variation due high-k dielectric investigated reviewing an antenna ratio distribution reported so far. Finally, concerns as future perspective—PPD a fin-structured FET Time-Dependent Dielectric Breakdown (TDDB) characterization. Since intrinsic nature processing, enhancement should be taken into account for Very-Large-Integration (VLSI) circuit designs.