Partial carry-save pipeline multiplier

作者: Yi-Feng Jang , Ching-Hsiang Yang , Po-Chuan Huang

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摘要: A pipeline multiplier is used for multiplying a multiplicand to multiplier. The includes plurality of adder stages each stage partial product processor processing the and one Each further ripple carry (RCA) bands band full adders wherein sequentially most significant in RCA band. Furthermore, approximately same number adders. are arranged sequential order such that pipelined corresponding band, which being more-significantly-shifted by bit, next according whereby an accumulative propagated from stage. add means last order. half adding bit least more propagating processed band-carry as carry-in.

参考文章(4)
Eiichi Nishimura, Hisaki Ishida, Takao Nakamura, Low-power parallel multiplier ,(1989)
Tai Sato, MOS array multiplier cell ,(1991)