作者: Robert Nathan
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摘要: Multiplier units of the modified Booth decoder and carry-save adder/full adder combination are used to implement a pipeline active filter wherein pixel data is processed sequentially, each need only be accessed once multiplied by predetermined number weights simultaneously, one multiplier unit for weight. Each uses row adders, results shifted less significant positions full adders add carry sum in order provide correct binary product Wp. The also this Wp products ΣWp from preceding multiply units. If m×m pipelined, system would capable processing kernel array weighting factors.