Fast multiplierless architecture for general purpose VLSI FIR digital filters with minimized hardware

摘要: A digital transversal filter which employs a multiplierless algorithm for effecting convolutions of samples input word by the coefficients. Each an is bit sliced into segments two or more bits, and are carried out in parallel on all using only adders registers. The convolution products then summed pipeline adder tree to derive complete word. This architecture provides high frequency capability significantly lower transistor count hardware complexity, enabling efficient very large scale integration (VLSI) implementation.