Monolithic discrete-time digital convolution circuit

摘要: A monolithic convolver circuit making extensive use of "pipelined" architecture to ensure high speed by concurrency processing, and having a repetitive stage facilitate chip layout manufacture. The includes multiplier an adder in each stage. adders produce sequence summation terms concurrently include shift registers move accumulate the results convolution. only partial sums at stage, increase processing speed. Full computation carries is deferred until very end, performed separate conditional sum adder.