Low power hardware implementations for network packet processing elements

摘要: Abstract The real world network packet processing demands high performance hardware to achieve the required speed. This paper proposes various optimizations on payload matching, classification, and backplane switch interconnects by allowing architectural changes in existing designs. Here, asynchronous Bloom filter based matching look up/decision tree classification with clock gating are proposed reduce switching power dissipations Also, this a new crossbar 2-to-1 multiplexer buffered performance. Our avoids tri-state buffer cross points due their contention issues larger circuits. All these designs implemented 45 n m CMOS technology. synthesis results show that significant improvement reduction over match architecture achieves 94.9 % of PDP Cuckoo design [5]. Similarly, 4 × 57.8 than [17].