A hierarchical approach towards system level static timing verification of SoCs

摘要: The high complexity and the core diversities make timing verification of an entire flattened SoC design a tedious process. In this paper, at first various issues related to modular have been investigated then bottom-up hierarchical approach verifying system level SoC, is presented. abstractions cores are assumed be provided by vendors. interconnection delays may extracted from SDF file generated after post layout simulation. provides fast systematic way verification, as opposed approach. Experiments were conducted on synthetic SoCs, using ISCAS benchmark circuits cores. Results validate claim proposed