Raising the Level of Abstraction for the Timing Verification of System-on-Chips
作者： Rupsa Chakraborty , Dipanwita Roy Chowdhury
关键词: Very-large-scale integration 、 Formal verification 、 Computer science 、 Embedded system 、 Place and route 、 Benchmark (computing) 、 Network analysis 、 Abstraction (linguistics) 、 Graph (abstract data type) 、 System on a chip
摘要: This paper proposes a general system-level timing verification method for System-on-Chips (SoC). Experiments have been carried out on several synthetic benchmark SoCs. Delays at the various interconnects are extracted from SDF file generated after place and route. A graph of cores is each SoC, with delays back annotated as weights. Algorithms presented that verifies criteria check points in circuit.
sci-hub.se 参考文章(5)
O. Maler, S. Yovine, Hardware timing verification using KRONOS Proceedings of the Seventh Israeli Conference on Computer Systems and Software Engineering. pp. 23- 29 ,(1996) , 10.1109/ICCSSE.1996.554845
Daniel Ferrao, Gustavo Wilke, Ricardo Reis, Carolina Neves, Luciano Agostini, Jose Guntzel, Safe Path-Based Hierarchical Functional Timing Analysis by Considering Block Arrival Times international caribbean conference on devices, circuits and systems. pp. 345- 349 ,(2006) , 10.1109/ICCDCS.2006.250885
A.J. Daga, W.P. Birmingham, A symbolic-simulation approach to the timing verification of interacting FSMs international conference on computer design. pp. 584- 589 ,(1995) , 10.1109/ICCD.1995.528927
H. Eriksson, P. Larsson-Edefors, D. Eckerbert, Toward architecture-based test-vector generation for timing verification of fast parallel multipliers IEEE Transactions on Very Large Scale Integration Systems. ,vol. 14, pp. 370- 379 ,(2006) , 10.1109/TVLSI.2006.874297
V. Vankamamidi, F. Lombardi, M. Ottavi, L. Schiano, S. Pontarelli, Timing Verification of QCA Memory Architectures international conference on nanotechnology. ,vol. 1, pp. 391- 394 ,(2006) , 10.1109/NANO.2006.247659